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Philips Semiconductors
Product specification
TrenchMOSTM transistor Standard level FET
GENERAL DESCRIPTION
N-channel enhancement mode standard level field-effect power transistor in a plastic envelope suitable for surface mounting. Using 'trench' technology, the device features very low on-state resistance and has integral zener diodes giving ESD protection up to 2kV. It is intended for use in DC-DC converters and general purpose switching applications.
PHT6N03T
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Tsp = 25 C Drain current (DC) Tamb = 25 C Total power dissipation Junction temperature Drain-source on-state resistance VGS = 10 V MAX. 30 12.8 5.9 8.3 150 30 UNIT V A A W C m
PINNING - SOT223
PIN 1 2 3 4 gate drain source drain (tab) DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
d
g s
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 k Tsp = 25 C Tamb = 25 C Tsp = 100 C Tamb = 100 C Tsp = 25 C Tamb = 25 C Tsp = 25 C Tamb = 25 C MIN. - 55 MAX. 30 30 16 12.8 5.9 9 4.1 51.2 23.6 8.3 1.8 150 UNIT V V V A A A A A A W W C
THERMAL RESISTANCES
SYMBOL Rth j-sp Rth j-amb PARAMETER Thermal resistance junction to solder point Thermal resistance junction to ambient CONDITIONS Mounted on any PCB Mounted on PCB of Fig.19 TYP. 12 MAX. 15 70 UNIT K/W K/W
November 1997
1
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOSTM transistor Standard level FET
ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage, all pins CONDITIONS Human body model (100 pF, 1.5 k) MIN. -
PHT6N03T
MAX. 2
UNIT kV
STATIC CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS V(BR)GSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 150C Tj = -55C VDS = 30 V; VGS = 0 V; VGS = 10 V; VDS = 0 V Tj = 150C Tj = 150C Tj = 150C MIN. 30 27 2.0 1.0 16 TYP. 3.0 0.05 0.02 24 MAX. 4.0 4.4 10 500 1 20 30 51 UNIT V V V V A A A A V m m
Gate source breakdown voltage IG = 1 mA; Drain-source on-state VGS = 10 V; ID = 3.2 A resistance
DYNAMIC CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL gfs Qg(tot) Qgs Qgd Ciss Coss Crss td on tr td off tf Ld Ld Ls PARAMETER Forward transconductance Total gate charge Gate-source charge Gate-drain (Miller) charge Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 5.9 A ID = 5.9 A; VDD = 24 V; VGS = 10 V MIN. 5 TYP. 10 22.5 4.5 13.5 1500 370 170 16 30 35 25 3.5 4.5 7.5 MAX. 2000 470 250 22 60 50 38 UNIT S nC nC nC pF pF pF ns ns ns ns nH nH nH
VGS = 0 V; VDS = 25 V; f = 1 MHz
VDD = 15 V; ID = 5.9 A; VGS = 10 V; RG = 5 Resistive load Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad
November 1997
2
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOSTM transistor Standard level FET
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 3.2 A; VGS = 0 V IF = 5.9 A; VGS = 0 V IF = 5.9 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 25 V TYP. 0.75 0.85 115 0.3
PHT6N03T
MAX. 6.2 24.8 1.2 -
UNIT A A V ns C
AVALANCHE LIMITING VALUE
SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 5.9 A; VDD 25 V; VGS = 10 V; RGS = 50 ; Tsp = 25 C MIN. TYP. MAX. 60 UNIT mJ
November 1997
3
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOSTM transistor Standard level FET
PHT6N03T
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
1E+02
Zth j-amb / (K/W)
BUKX83
D= 0.5
0.2 0.1 0.05 0.02
P D tp D= tp T
1E+01
1E+00
1E-01 0
T t
0
20
40
60
80 100 Tmb / C
120
140
1E-02 1E-07
1E-05
1E-03 t/s
1E-01
1E+01
1E+03
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
ID% Normalised Current Derating
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
ID / A 12 10 8 50 40 30 6 20 10 0 5.5 5 4.5 4 0 2 4 VDS / V 6 8 10 VGS / V = 6.5
120 110 100 90 80 70 60 50 40 30 20 10 0
60
BUK7830-30
0
20
40
60
80 Tmb / C
100
120
140
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 10 V
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS
RDS(ON) / mOhm 6 6.5
100
ID / A
DS / ID
7830-30
6 5
7830-30 8
10
R
( DS
) ON
=V
tp = 10 us 100 us
4 3 2 1
10 12 VGS / V =
1 DC
1 ms 10 ms
0.1
100 ms
0.01 0.1
1
10 VDS / V
100
1000
0
0
10
20
30 ID / A
40
50
60
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS
November 1997
4
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOSTM transistor Standard level FET
PHT6N03T
60 50 40 30
ID / A
7830-30 Tj / C = 25
5
VGS(TO) / V max.
BUK759-60
4
150
3
typ.
min. 2
20 10 0
1
0
2
4 VGS / V
6
8
10
0 -100
-50
0
50 Tj / C
100
150
200
Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
gfs / S 7830-30
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Sub-Threshold Conduction
15
1E-01
1E-02
10
Tj / C = 25 150
1E-03 2% typ 98%
5
1E-04
1E-05
0
0
10
20
30 ID / A
40
50
60
1E-06
0
1
2
3
4
5
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V
a
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
C / pF 7528-30
2
SOT223 30V Trench
Normalised RDS(ON) = f(Tj)
10000
1.5
Ciss
1
1000
0.5
Coss Crss
0 -50
0
50 Tj / C
100
150
100 0.1
1 VDS / V
10
100
Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 3.2 A; VGS = 10 V
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
November 1997
5
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOSTM transistor Standard level FET
PHT6N03T
10
VGS / V
7830-30
120 110 100 90 80 70 60 50 40 30 20 10 0
WDSS%
8
VDS / V = 6
24
6
4
2
0
0
5
10 QG / nC
15
20
25
20
40
60
80 100 Tmb / C
120
140
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 5.9 A; parameter VDS
IF / A
Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 5.9 A
60 50 40 30 20 10 0
7830-30
+
L VDS VGS 0
Tj / C = 150 25
VDD
-ID/100 T.U.T. R 01 shunt
RGS
0
0.5
1 VSDS / V
1.5
2
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD )
+
RD VDS VGS 0 RG T.U.T.
VDD
-
Fig.17. Switching test circuit.
November 1997
6
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOSTM transistor Standard level FET
MOUNTING INSTRUCTIONS
PHT6N03T
Dimensions in mm.
3.8 min
1.5 min
2.3 1.5 min (3x)
6.3
1.5 min
4.6
Fig.18. soldering pattern for surface mounting SOT223.
November 1997
7
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOSTM transistor Standard level FET
PRINTED CIRCUIT BOARD
PHT6N03T
Dimensions in mm.
36
18
60 9 4.6 4.5
10
7 15 50
Fig.19. PCB for thermal resistance and power rating for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 m thick).
November 1997
8
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOSTM transistor Standard level FET
MECHANICAL DATA
Dimensions in mm Net Mass: 0.11 g
0.32 0.24 6.7 6.3 3.1 2.9 B
PHT6N03T
0.2
M
A
4
A
0.10 0.02
3.7 3.3 13
7.3 6.7
16 max
1
10 max 1.8 max 1.05 0.85 4.6 2.3
2
0.80 0.60
3
0.1 M (4x) B
Fig.20. SOT223 surface mounting package.
Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to surface mounting instructions for SOT223 envelope. 3. Epoxy meets UL94 V0 at 1/8".
November 1997
9
Rev 1.200
Philips Semiconductors
Product specification
TrenchMOSTM transistor Standard level FET
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
PHT6N03T
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
November 1997
10
Rev 1.200

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